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ADE7932 数据表(PDF) 104 Page - Analog Devices

部件名 ADE7932
功能描述  Isolated Energy Metering Chipset for Polyphase Shunt Meters
PDF  120 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADE7932 数据表(HTML) 104 Page - Analog Devices

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ADE7978/ADE7933/ADE7932
Data Sheet
Rev. 0 | Page 104 of 120
Address
Register
Name
R/W1
Bit
Length
Bit Length During
Communication2
Type3
Default
Value4
Description
0xE700
MMODE
R/W
8
8
U
0x1C
Measurement mode register (see Table 54).
0xE701
ACCMODE
R/W
8
8
U
0x00
Accumulation mode register (see Table 55).
0xE702
LCYCMODE
R/W
8
8
U
0x78
Line accumulation mode behavior (see
Table 57).
0xE703
PEAKCYC
R/W
8
8
U
0x00
Peak detection half line cycles.
0xE704
SAGCYC
R/W
8
8
U
0x00
Sag detection half line cycles.
0xE705
CFCYC
R/W
8
8
U
0x01
Number of CF pulses between two
consecutive energy latches (see the
Synchronizing Energy Registers with the
CFx Outputs section).
0xE706
HSDC_CFG
R/W
8
8
U
0x00
HSDC configuration register (see Table 58).
0xE707
Version
R
8
8
U
Version of die.
0xE708
CONFIG3
R/W
8
8
U
0x0F
ADE7933/ADE7932 configuration register
(see Table 59).
0xE709
ATEMPOS
R
8
8
S
0x00
Phase A ADE7933/ADE7932 temperature
sensor offset.
0xE70A
BTEMPOS
R
8
8
S
0x00
Phase B ADE7933/ADE7932 temperature
sensor offset.
0xE70B
CTEMPOS
R
8
8
S
0x00
Phase C ADE7933/ADE7932 temperature
sensor offset.
0xE70C
NTEMPOS
R
8
8
S
0x00
Neutral line ADE7933/ADE7932 temperature
sensor offset.
0xE70D
to
0xE7E2
Reserved
These addresses should not be written for
proper operation.
0xE7E3
Reserved
R/W
8
8
U
N/A
Internal register used in conjunction with
the internal register at Address 0xE7FE to
enable/disable the protection of the DSP
RAM-based registers (see the Digital Signal
Processor section for more information).
0xE7E4
to
0xE7FC
Reserved
These addresses should not be written for
proper operation.
0xE7FD
LAST_
RWDATA8
R
8
8
U
N/A
Contains the data from the last successful
8-bit register communication.
0xE7FE
Reserved
R/W
8
8
U
N/A
Internal register used in conjunction with
the internal register at Address 0xE7E3 to
enable/disable the protection of the DSP
RAM-based registers (see the Digital Signal
Processor section for more information).
0xE7FF
to
0xE901
Reserved
These addresses should not be written for
proper operation.
0xE902
APF
R
16
16
U
N/A
Phase A power factor.
0xE903
BPF
R
16
16
U
N/A
Phase B power factor.
0xE904
CPF
R
16
16
U
N/A
Phase C power factor.
0xE905
APERIOD
R
16
16
U
N/A
Line period on Phase A voltage.
0xE906
BPERIOD
R
16
16
U
N/A
Line period on Phase B voltage.
0xE907
CPERIOD
R
16
16
U
N/A
Line period on Phase C voltage.
0xE908
APNOLOAD
R/W
16
16
U
0x0000
No load threshold in the total/fundamental
active power datapath.
0xE909
VARNOLOAD
R/W
16
16
U
0x0000
No load threshold in the total/fundamental
reactive power datapath.
0xE90A
VANOLOAD
R/W
16
16
U
0x0000
No load threshold in the apparent power
datapath.



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