ADE7932 datasheet(107/120 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 107 of 120

Table 44. STATUS1 Register (Address 0xE503)

Bits

Bit Name

Default Value

Description

NLOAD

When this bit is set to 1, it indicates that at least one phase entered or exited the no load

condition based on the total active and reactive powers. The phase is indicated in Bits[2:0]

(NLPHASE[x]) in the PHNOLOAD register (see Table 48).

FNLOAD

When this bit is set to 1, it indicates that at least one phase entered or exited the no load

condition based on the fundamental active and reactive powers. The phase is indicated in

Bits[5:3] (FNLPHASE[x]) in the PHNOLOAD register (see Table 48).

VANLOAD

When this bit is set to 1, it indicates that at least one phase entered or exited the no load

condition based on the apparent power. The phase is indicated in Bits[8:6] (VANLPHASE[x])

in the PHNOLOAD register (see Table 48).

ZXTOVA

When this bit is set to 1, it indicates that a zero crossing on the Phase A voltage is missing.

ZXTOVB

When this bit is set to 1, it indicates that a zero crossing on the Phase B voltage is missing.

ZXTOVC

When this bit is set to 1, it indicates that a zero crossing on the Phase C voltage is missing.

ZXTOIA

When this bit is set to 1, it indicates that a zero crossing on the Phase A current is missing.

ZXTOIB

When this bit is set to 1, it indicates that a zero crossing on the Phase B current is missing.

ZXTOIC

When this bit is set to 1, it indicates that a zero crossing on the Phase C current is missing.

ZXVA

When this bit is set to 1, it indicates that a zero crossing was detected on the Phase A voltage.

ZXVB

When this bit is set to 1, it indicates that a zero crossing was detected on the Phase B voltage.

ZXVC

When this bit is set to 1, it indicates that a zero crossing was detected on the Phase C voltage.

ZXIA

When this bit is set to 1, it indicates that a zero crossing was detected on the Phase A current.

ZXIB

When this bit is set to 1, it indicates that a zero crossing was detected on the Phase B current.

ZXIC

When this bit is set to 1, it indicates that a zero crossing was detected on the Phase C current.

RSTDONE

At the end of a hardware or software reset, this bit is set to 1, and the IRQ1 pin goes low.

To clear this interrupt and return the IRQ1 pin high, write a 1 to this bit. The RSTDONE

interrupt cannot be masked; therefore, this bit must always be reset to 0 for the IRQ1 pin

to return high.

Sag

When this bit is set to 1, it indicates that a sag event occurred on the phase indicated by

Bits[14:12] (VSPHASE[x]) in the PHSTATUS register (see Table 47).

When this bit is set to 1, it indicates that an overcurrent event occurred on the phase

indicated by Bits[5:3] (OIPHASE[x]) in the PHSTATUS register (see Table 47).

When this bit is set to 1, it indicates that an overvoltage event occurred on the phase

indicated by Bits[11:9] (OVPHASE[x]) in the PHSTATUS register (see Table 47).

SEQERR

When this bit is set to 1, it indicates that a negative to positive zero crossing on the

Phase A voltage was followed by a negative to positive zero crossing on the Phase C

voltage instead of on the Phase B voltage.

MISMTCH

When this bit is set to 1, it indicates that ||ISUM| − |INWV|| > |ISUMLVL|, where ISUMLVL is

the value of the ISUMLVL register (Address 0x4398). For more information, see the Neutral

Current Mismatch section.

Reserved

Reserved. This bit is always set to 1.

Reserved

Reserved. This bit is always set to 0.

PKI

When this bit is set to 1, it indicates that the period used to detect the peak value in the

current channel has ended. The IPEAK register contains the peak value and the phase

where the peak was detected (see Table 41).

PKV

When this bit is set to 1, it indicates that the period used to detect the peak value in the

voltage channel has ended. The VPEAK register contains the peak value and the phase

where the peak was detected (see Table 42).

CRC

When this bit is set to 1, it indicates that the ADE7978 has computed a checksum value

that is different from the checksum value computed when the run register was set to 1.

[31:26]

Reserved

00 0000

Reserved. These bits are always set to 0.

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