ADE7932 datasheet(115/120 Pages) AD

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Data Sheet

ADE7978/ADE7933/ADE7932

Rev. 0 | Page 115 of 120

Table 54. MMODE Register (Address 0xE700)

Bits

Bit Name

Default Value

Description

REVAPSEL

This bit specifies whether the total active power or the fundamental active power on

Phase A, Phase B, or Phase C is used to trigger a bit in the STATUS0 register. Phase A triggers

Bit 6 (REVAPA), Phase B triggers Bit 7 (REVAPB), and Phase C triggers Bit 8 (REVAPC).

0: The total active power is used to trigger the bits in the STATUS0 register.

1: The fundamental active power is used to trigger the bits in the STATUS0 register.

REVRPSEL

This bit specifies whether the total reactive power or the fundamental reactive power on

Phase A, Phase B, or Phase C is used to trigger a bit in the STATUS0 register. Phase A triggers

Bit 10 (REVRPA), Phase B triggers Bit 11 (REVRPB), and Phase C triggers Bit 12 (REVRPC).

0: The total reactive power is used to trigger the bits in the STATUS0 register.

1: The fundamental reactive power is used to trigger the bits in the STATUS0 register.

PEAKSEL[0]

0: Phase A is not included in the voltage and current peak detection.

1: Phase A is included in the voltage and current peak detection.

PEAKSEL[1]

0: Phase B is not included in the voltage and current peak detection.

1: Phase B is included in the voltage and current peak detection.

PEAKSEL[2]

0: Phase C is not included in the voltage and current peak detection.

1: Phase C is included in the voltage and current peak detection.

[7:5]

Reserved

000

Reserved. These bits do not manage any functionality.

Table 55. ACCMODE Register (Address 0xE701)

Bits

Bit Name

Default Value

Description

[1:0]

WATTACC[1:0]

These bits determine how the active power is accumulated in the watthour registers and

how the CFx frequency output is generated as a function of the total and fundamental

active powers.

00: signed accumulation mode of the total and fundamental active powers. The active

energy registers and the CFx pulses are generated in the same way.

01: positive only accumulation mode of the total and fundamental active powers. The total

and fundamental active energy registers are accumulated in positive only mode, but the

CFx pulses are generated in signed accumulation mode.

10: reserved (same as WATTACC[1:0] = 00).

11: absolute accumulation mode of the total and fundamental active powers. The total and

fundamental active energy registers and the CFx pulses are generated in the same way.

[3:2]

VARACC[1:0]

These bits determine how the reactive power is accumulated in the var-hour registers and

how the CFx frequency output is generated as a function of the total and fundamental

active and reactive powers.

00: signed accumulation mode of the total and fundamental reactive powers. The reactive

energy registers and the CFx pulses are generated in the same way.

01: reserved (same as VARACC[1:0] = 00).

10: the total and fundamental reactive powers are accumulated depending on the sign of

the total and fundamental active powers. If the active power is positive, the reactive power

is accumulated as is; if the active power is negative, the reactive power is accumulated with a

reversed sign. The total and fundamental reactive energy registers and the CFx pulses are

generated in the same way.

11: absolute accumulation mode of the total and fundamental reactive powers. The total and

fundamental reactive energy registers and the CFx pulses are generated in the same way.

[5:4]

CONSEL[1:0]

These bits select the inputs to the energy accumulation registers. IA’, IB’, and IC’ are IA, IB,

and IC shifted by −90° (see Table 56).

00: 3-phase, 4-wire with three voltage sensors.

01: 3-phase, 3-wire delta connection.

10: reserved.

11: 3-phase, 4-wire delta connection.

SAGCFG

This bit manages how the sag flag status bit in the STATUS1 register is generated.

0: the flag is set to 1 when any phase voltage is below the SAGLVL threshold.

1: the flag is set to 1 when any phase voltage goes below and then above the SAGLVL

threshold.

Reserved

Reserved. This bit does not manage any functionality.

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