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ADE7932 数据表(PDF) 116 Page - Analog Devices |
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ADE7932 数据表(HTML) 116 Page - Analog Devices |
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116 / 120 page  ADE7978/ADE7933/ADE7932 Data Sheet Rev. 0 | Page 116 of 120 Table 56. CONSEL[1:0] Bits in Energy Registers1 Energy Registers CONSEL[1:0] = 00 CONSEL[1:0] = 01 CONSEL[1:0] = 11 AWATTHR, AFWATTHR VA × IA VA × IA VA × IA BWATTHR, BFWATTHR VB × IB VB = VA − VC VB = −VA VB × IB1 VB × IB CWATTHR, CFWATTHR VC × IC VC × IC VC × IC AVARHR, AFVARHR VA × IA’ VA × IA’ VA × IA’ BVARHR, BFVARHR VB × IB’ VB = VA − VC VB = −VA VB × IB’1 VB × IB’ CVARHR, CFVARHR VC × IC’ VC × IC’ VC × IC’ AVAHR VA rms × IA rms VA rms × IA rms VA rms × IA rms BVAHR VB rms × IB rms VB rms × IB rms1 VB rms × IB rms VB = VA − VC VB = −VA CVAHR VC rms × IC rms VC rms × IC rms VC rms × IC rms 1 In a 3-phase, 3-wire configuration (CONSEL[1:0] = 01), the ADE7978 computes the rms value of the line voltage between Phase A and Phase C and stores the result in the BVRMS register (see the Voltage RMS in Delta Configurations section). The Phase B current value provided after the HPF is 0. Consequently, the powers associated with Phase B are 0. To avoid any errors in the frequency output pins (CF1, CF2, or CF3) related to the powers associated with Phase B, disable the contribution of Phase B to the energy-to-frequency converters by setting the TERMSEL1[1], TERMSEL2[1], or TERMSEL3[1] bit to 0 in the COMPMODE register. For more information, see the Energy-to-Frequency Conversion section. Table 57. LCYCMODE Register (Address 0xE702) Bits Bit Name Default Value Description 0 LWATT 0 0: the watthour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR, BFWATTHR, and CFWATTHR) are configured for regular accumulation mode. 1: the watthour accumulation registers (AWATTHR, BWATTHR, CWATTHR, AFWATTHR, BFWATTHR, and CFWATTHR) are configured for line cycle accumulation mode. 1 LVAR 0 0: the var-hour accumulation registers (AVARHR, BVARHR, CVARHR, AFVARHR, BFVARHR, and CFVARHR) are configured for regular accumulation mode. 1: the var-hour accumulation registers (AVARHR, BVARHR, CVARHR, AFVARHR, BFVARHR, and CFVARHR) are configured for line cycle accumulation mode. 2 LVA 0 0: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are configured for regular accumulation mode. 1: the VA-hour accumulation registers (AVAHR, BVAHR, and CVAHR) are configured for line cycle accumulation mode. 3 ZXSEL[0] 1 0: Phase A is not selected for zero-crossing counts in line cycle accumulation mode. 1: Phase A is selected for zero-crossing counts in line cycle accumulation mode. If more than one phase is selected for zero-crossing detection, the accumulation time is shortened accordingly. 4 ZXSEL[1] 1 0: Phase B is not selected for zero-crossing counts in line cycle accumulation mode. 1: Phase B is selected for zero-crossing counts in line cycle accumulation mode. If more than one phase is selected for zero-crossing detection, the accumulation time is shortened accordingly. 5 ZXSEL[2] 1 0: Phase C is not selected for zero-crossing counts in line cycle accumulation mode. 1: Phase C is selected for zero-crossing counts in line cycle accumulation mode. If more than one phase is selected for zero-crossing detection, the accumulation time is shortened accordingly. 6 RSTREAD 1 0: disables read with reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR registers. Clear this bit to 0 when Bits[2:0] (LVA, LVAR, and LWATT) are set to 1. 1: enables read with reset of all xWATTHR, xVARHR, xVAHR, xFWATTHR, and xFVARHR registers. When this bit is set to 1, a read of these registers resets them to 0. 7 PFMODE 0 0: power factor calculation uses instantaneous values of various phase powers used in its expression. 1: power factor calculation uses phase energy values calculated using line cycle accumula- tion mode. The LWATT and LVA bits (Bit 0 and Bit 2) must be enabled for the power factors to be computed correctly. The update rate of the power factor measurement is the integral number of half line cycles that is programmed in the LINECYC register. |
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