RM0352 datasheet(109/138 Pages) STMICROELECTRONICS

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RM0352

SPI (serial peripheral interface)

137

11.4.9

Interrupt clear register, SSPICR

The SSPICR register characteristics are:

Purpose

The SSPICR register is the interrupt clear register and is write-only.

On a write of 1, the corresponding interrupt is cleared. A write of 0

has no effect.

Usage constraints

There are no usage constraints.

Configurations

Available in all SSP configurations.

Attributes

See

Table 96 on page 101.

Table 105 shows the bit assignment.

11.4.10

Peripheral identification registers, SSPPeriphID0-3

The SSPPeriphID0-3 registers characteristics are:

Note:

When you design a system memory map, you must remember that the register has a 4 KB-

memory footprint. All memory accesses to the peripheral identification registers must be

32-bit, using the LDR and STR instructions.

Table 105. SSPICR register bit assignments

Bits

Name

Function

[15:2]

RESERVED

RESERVED, read as zero, do not modify

[1]

RTIC

Clears the SSPRTINTR interrupt

[0]

RORIC

Clears the SSPRORINTR interrupt

Purpose

The SSPPeriphID0-3 registers are four 8-bit registers, that span

address locations 0xFE0 to 0xFEC. The registers can conceptually

be treated as a single 32-bit register. The RO registers provide the

following options for the peripheral:

PartNumber[11:0]

This is used to identify the peripheral. The three digits product code

0x022 is used.

Designer ID[19:12]

This is the identification of the designer. ARM Ltd is 0x41, ASCII A.

Revision[23:20]

This is the revision number of the peripheral. The number starts

from 0 and is revision dependent.

Configuration[31:24]

This is the configuration option of the peripheral. The configuration

value is 0.

Usage constraints

There are no usage constraints.

Configurations

Available in all SSP configurations.

Attributes

See

Table 96 on page 101.

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