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RM0352 数据表(PDF) 112 Page - STMicroelectronics |
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RM0352 数据表(HTML) 112 Page - STMicroelectronics |
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112 / 138 page  SPI (serial peripheral interface) RM0352 112/138 DocID024647 Rev 1 The following subsections describe the four, 8-bit PrimeCell identification registers: • SSPPCellID0 register • SSPPCellID1 register • SSPPCellID2 register • SSPPCellID3 register SSPPCellID0 register The SSPPCellID0 register characteristics are: Purpose The SSPPCellID0 register is hard-coded and the fields within the register determine the reset value. Usage constraints There are no usage constraints. Configurations Available in all SSP configurations. Attributes See Table 96 on page 101. Table 110 shows the bit assignments. SSPPCellID1 register The SSPPCellID1 register characteristics are: Purpose The SSPPCellID1 register is hard-coded and the fields within the register determine the reset value. Usage constraints There are no usage constraints. Configurations Available in all SSP configurations. Attributes See Table 96 on page 101. Table 111 shows the bit assignments. SSPPCellID2 register The SSPPCellID2 register characteristics are: Purpose The SSPPCellID2 register is hard-coded and the fields within the register determine the reset value. Usage constraints There are no usage constraints. Table 110. SSPPCellID0 register bit assignments Bits Name Description [15:8] RESERVED RESERVED, read undefined, must read as zeros [7:0] SSPPCellID0 These bits read back as 0x0D Table 111. SSPPCellID1 register bit assignments Bits Name Description [15:8] RESERVED RESERVED, read undefined, must read as zeros [7:0] SSPPCellID1 These bits read back as 0xF0 |
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