RM0352 datasheet(118/138 Pages) STMICROELECTRONICS

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UART (universal asynchronous receive transmit)

RM0352

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DocID024647 Rev 1

To update the transmit FIFO you must:

•

Write data to the transmit FIFO, either prior to enabling the UART and the interrupts, or

after enabling the UART and interrupts.

Note:

The transmit interrupt is based on a transition through a level, rather than on the level itself.

When the interrupt and the UART is enabled before any data is written to the transmit FIFO

the interrupt is not set. The interrupt is only set, after written data leaves the single location

of the transmit FIFO and it becomes empty.

12.4.4

UARTRTINTR

The receive timeout interrupt is asserted when the receive FIFO is not empty, and no more

data is received during a 32-bit period. The receive timeout interrupt is cleared either when

the FIFO becomes empty through reading all the data (or by reading the holding register), or

when a 1 is written to the corresponding bit of the interrupt clear register, UARTICR - see

Section 12.6.13 on page 133.

12.4.5

UARTEINTR

The error interrupt is asserted when an error occurs in the reception of data by the UART.

The interrupt can be caused by a number of different error conditions:

•

Framing

•

Parity

•

Break

•

Overrun

The cause of the interrupt is visible by reading the raw interrupt status register, UARTRIS -

see

Section 12.6.11 on page 131 or the masked interrupt status register, UARTMIS - see

Section 12.6.12 on page 132. It can be cleared by writing to the relevant bits of the interrupt

clear register, UARTICR - see

Section 12.6.13 on page 133 (bits 7 to 10 are the error clear

bits).

12.4.6

UARTINTR

The interrupts are also combined into a single output, that is an OR function of the individual

masked sources. This output is connected to the “Nested Vector Interrupt Controller” (NVIC)

to provide another level of masking on a individual peripheral basis (see

Table 3 on page 17.

The combined UART interrupt is asserted if any of the individual interrupts are asserted and

enabled.

12.5

UART registers

The UART base address block in the Brain memory map is 0xA200_0000.

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