RM0352 datasheet(123/138 Pages) STMICROELECTRONICS

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RM0352

UART (universal asynchronous receive transmit)

137

12.6.4

IrDA low-power counter register, UARTILPR

The UARTILPR register is the IrDA low-power counter register. This is an 8-bit read/write

IrLPBaud16

signal by dividing down of

UARTCLK. Table 118 lists the register bit assignments.

5TXFF

Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H

If the FIFO is disabled, this bit is set when the transmit holding register is full.

If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.

RXFE

Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the

UARTLCR_H register.

If the FIFO is disabled, this bit is set when the receive holding register is empty.

If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.

BUSY

UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the

complete byte, including all the stop bits, has been sent from the shift register.

This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is

enabled or not.

DCD

Data carrier detect. This bit is the complement of the UART data carrier detect,

nUARTDCD,

modem status input. That is, the bit is 1 when

nUARTDCD is LOW.

DSR

Data set ready. This bit is the complement of the UART data set ready,

nUARTDSR, modem status

input. That is, the bit is 1 when

nUARTDSR is LOW.

CTS

Clear to send. This bit is the complement of the UART clear to send,

nUARTCTS, modem status

input. That is, the bit is 1 when

nUARTCTS is LOW.

Table 117. UARTFR register (continued)

Bits

Name

Function

Table 118. UARTILPR register

Bits

Name

Function

7:0

ILPDVSR

8-bit low-power divisor value. These bits are cleared to 0 at reset.

(1)

The IrLPBaud16 signal is generated by dividing down the

UARTCLK signal according to the

low-power divisor value written to the UARTILPR register.

The low-power divisor value is calculated as follows:

low-power divisor (ILPDVSR) = (F

UARTCLK

/ F

IrLPBaud16

)

where

FIrLPBaud16 is nominally 1.8432 MHz.

You must select the divisor so that 1.42 MHz <

FIrLPBaud16 < 2.12 MHz, results in a low-

power pulse duration of 1.41 - 2.11 μs (three times the period of

IrLPBaud16)(2).

Zero is an illegal value. Programming a zero value results in no

IrLPBaud16 pulses being generated.

In low-power IrDA mode the UART rejects random noise on the received serial data input by ignoring

SIRIN pulses that are

less than 3 periods of

IrLPBaud16.

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