RM0312 datasheet(117/275 Pages) STMICROELECTRONICS

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RM0312

16-bit general purpose timer (TIM2/TIM3)

170

When a rising edge occurs on TI2, the counter counts once and the trigger flag is set (TIF bit

in the TIMx_SR1 register) and an interrupt request can be sent if enabled (depending on the

TIE in TIMx_IER register).

The delay between the rising edge on TI2 and the actual reset of the counter is due to the

resynchronization circuit on TI2 input.

Figure 33. Control circuit in external clock mode 1

17.4.4

External clock source mode 2

The counter can count at each rising or falling edge on the external trigger input ETR. This

mode is selected by writing ECE=1 in the TIMx_ETR register.

The Figure 34 gives an overview of the external trigger input block.

Figure 34. External trigger input block

For example, to configure the up-counter to count each 2 rising edges on ETR, use the

following procedure:

As no filter is needed in this example, write ETF[3:0]=0b0000 in the TIMx_ETR register.

Set the prescaler by writing ETPS[1:0]=0b01 in the TIMx_ETR register

Select rising edge detection on the TRIG pin by writing ETP=0 in the TIMx_ETR

Enable external clock mode 2 by writing ECE=1 in the TIMx_ETR register.

Enable the counter by writing CEN=1 in the TIMx_CR1 register.

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER

TI2

CNT_EN

TIF

Write TIF=0

ETR

TIMx_ETR

ETP

divider

/1, /2, /4, /8

ETPS[1:0]

ETRP

filter

ETF[3:0]

down-counter

fMASTER

TIMx_ETR

TRIG pin

fMASTER

encoder

mode

external clock

mode 1

external clock

mode 2

internal clock

mode

ETRF

TRGI

TI1F

TI2F

(internal clock)

CK_PSC

TIMx_ETR

ECE

TIMx_SMCR

SMS[2:0]

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