RM0312 datasheet(113/275 Pages) STMICROELECTRONICS

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RM0312

16-bit general purpose timer (TIM2/TIM3)

170

17.3.6

Center-aligned mode (up/down counting)

In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the

TIMx_ARR register) -1, generates a counter overflow event, then counts down to 0 and

generates a counter underflow event. Then it restarts counting from 0.

In this mode, the DIR direction bit in the TIMx_CR1 register cannot be written. It is updated

by hardware and gives the current direction of the counter.

The Figure 28 shows an example of this counting mode.

Figure 28. Counter in center-aligned mode

The update event is generated at each counter overflow and at each counter underflow.

Setting the bit UG in the TIMx_EGR register (by software or by using the clock/trigger mode

controller) also generates an update event. In this case, the counter restarts counting from

0, as well as the counter of the prescaler.

The update event (UEV) can be disabled by software setting the UDIS bit in TIMx_CR1

preload registers. Then no update event will occur until UDIS bit has been written to 0.

However, the counter continues counting up and down, based on the current auto-reload

value.

If the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit

generates an update event UEV but without setting the UIF flag (thus no interrupt request

will be sent). This is to avoid generating both update and capture interrupts when clearing

the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR1 register) is set (depending on the URS bit).

The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSCR

The auto-reload shadow register is updated with the preload value (content of the

TIMx_ARR register). Note that if the update source is a counter overflow, the auto-reload is

updated before the counter is reloaded, so that the next period is the expected one (the

counter is loaded with the new value).

Hereafter are some examples of the counter behavior for different clock frequencies.

Counter

Time

TIMx_ARR

Underflow

Overflow

Underflow

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