RM0312 datasheet(110/275 Pages) STMICROELECTRONICS

110 / 275 page

16-bit general purpose timer (TIM2/TIM3)

RM0312

110/275

DocID022352 Rev 3

Figure 23. Counter update when ARPE=0 (ARR not preloaded) with prescaler = 2

In Figure 24 the prescaler divider is set to 1, so CK_CNT has the same frequency as

CK_PSC.

In Figure 24 autoreload preload is enabled (ARPE=1), so the next counter overflow occurs

at FFh. The new autoreload value register value of 36h is taken into account after the

overflow which generates an update event.

Figure 24. Counter update event when ARPE=1 (TIMx_ARR preloaded)

CK_PSC

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER

UPDATE INTERRUPT FLAG (UIF)

COUNTER OVERFLOW

UPDATE EVENT (UEV)

01 02 03 04 05 06 07

32 33 34 35 36

AUTO-RELOAD PRELOAD REGISTER

AUTO-RELOAD SHADOW REGISTER

Write a new value in TIMx_ARR

New value transferred immediately in shadow register

CNT_EN

TIMER CLOCK = CK_CNT

COUNTER REGISTER

UPDATE INTERRUPT FLAG (UIF)

COUNTER OVERFLOW

UPDATE EVENT (UEV)

01 02 03 04 05 06 07

FB FC FD FE FF

AUTO-RELOAD PRELOAD REGISTER

AUTO-RELOAD SHADOW REGISTER

Write a new value in TIMx_ARR

CK_PSC

New value transferred in shadow register

on counter overflow

RM0312 数据表(PDF) 110 Page - STMicroelectronics

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