RM0312 datasheet(109/275 Pages) STMICROELECTRONICS

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RM0312

16-bit general purpose timer (TIM2/TIM3)

170

17.3.4

Up-counting mode

In up-counting mode, the counter counts from 0 to a user-defined compare value (content of

the TIMx_ARR register), then restarts from 0 and generates a counter overflow event, and

an update event (UEV) if the UDIS bit is 0 in the TIMx_CR1 register.

Figure 22 shows an example of this counting mode.

Figure 22. Counter in up-counting mode

An update event can also be generated by setting the bit UG in the TIMx_EGR register (by

software or by using the trigger controller).

The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1

preload registers. Then no update event will occur until UDIS bit has been written to 0.

However, the counter restarts from 0, as well as the counter of the prescaler (but the

prescaler division factor does not change). In addition, if the URS bit (update request

selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV

but without setting the UIF flag (thus no interrupt request is sent). This is to avoid generating

both update and capture interrupts when clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR1 register) is set (depending on the URS bit):

The auto-reload shadow register is updated with the preload value (TIMx_ARR),

The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSCR

The following figures show two examples of the counter behavior for different clock

frequencies when TIMx_ARR=36h.

In Figure 23 the prescaler divider is set to 2, so the counter clock (CK_CNT) frequency is at

half the frequency of the the prescaler clock source (CK_PSC).

In Figure 23 the autoreload preload is disabled (ARPE=0), so the shadow register is

changed immediately and counter overflow occurs when upcounting reaches 36h. This

generates an update event.

Counter

TIMx_ARR

Overflow

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