RM0312 datasheet(111/275 Pages) STMICROELECTRONICS

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RM0312

16-bit general purpose timer (TIM2/TIM3)

170

17.3.5

Down-counting mode

In down-counting mode, the counter counts from the auto-reload value (content of the

TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a

counter underflow and an update event (UEV) if the UDIS bit is 0 in the TIMx_CR1 register.

Figure 25 shows an example of this counting mode.

Figure 25. Counter in down-counting mode

An update event can also be generated by setting the bit UG in the TIMx_EGR register (by

software or by using the clock/trigger mode controller).

The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1

preload registers. Then no update event will occur until UDIS bit has been written to 0.

However, the counter restarts from the current auto-reload value, whereas the counter of the

prescaler restarts from 0 (but the prescale rate doesn’t change).

In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the

UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt

request is sent). This is to avoid generating both update and capture interrupts when

clearing the counter on the capture event.

When an update event occurs, all the registers are updated and the update flag (UIF bit in

TIMx_SR1 register) is set (depending on the URS bit):

The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSCR

The auto-reload shadow register is updated with the preload value (content of the

TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so

that the next period is the expected one.

The following figures show some examples of the counter behavior for different clock

frequencies when TIMx_ARR=36h.

In downcounting mode, preload is normally not used so that the new value is taken into

account in the next period (see Figure 26).

Counter

Time

TIMx_ARR

Underflow

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