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RM0319 数据表(PDF) 348 Page - STMicroelectronics

部件名 RM0319
功能描述  SPEAr320S architecture and functionality
PDF  368 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

RM0319 数据表(HTML) 348 Page - STMicroelectronics

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Watchdog timer (WDT)
RM0319
348/368
Doc ID 022640 Rev 3
Figure 115. Watchdog module block diagram
34.3.1
AMBA APB interface
The AMBA APB interface block provides an APB slave which allows to accesses to all
registers in the watchdog module.
In particular, the lock register (WdogLock) controls the enabling of write accesses to all the
other registers in order to ensure software cannot unintentionally disable the watchdog
module operation.
34.3.2
Free running counter
The free running counter block contains the 32-bit down counter functionality (including
related registers), and the logic to generate the interrupt and reset signal outputs.
The counter and the interrupt/reset logic are clocked independently, as detailed in
Section 34.4 on page 348.
34.4
Clocks
The watchdog module uses two different input clocks:
The clock of the APB bus (PCLK signal), which is used to clock the Watchdog module
registers through APB bus.
The external WDOGCLK signal which, in conjunction with its clock enable,
WGDOGCLKEN, is used to clock the Watchdog module counter and its associated
interrupt and reset generation logic. In particular, the watchdog counter only
decrements on a rising edge of WDOGCLK when WDOGCLKEN is HIGH.
The following constraints must be observed in the relationship between the two clocks:
The rising edge of WDOGCLK must be synchronous and balanced with the rising edge
of PCLK,
The WDOGCLK frequency cannot be greater than the PCLK frequency.
From the constraints above and depending on the relationship between WDOGCLK and
WDOGCLKEN, the watchdog module counter is decremented on different ways
summarized in Table 123.
Free Running
Counter
Load Register Control Register
32-bit down counter
Value Register
Interrupt and
Reset generation
Raw Interrupt Status Register
Masked Interrupt Status Register
Interrupt Clear Register
AMBA APB Interface
ID Registers
Lock Register
Integration Test Register
WDOGINT
WDOGRES
AMBA APB
Signals
WDOGCLK
WDOGCLKEN
WDOGRESn



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