PC87366 datasheet(107/240 Pages) NSC

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3.0 System Wake-Up Control (SWC) (Continued)

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3.4.23

CEIR Wake-Up Address Register (IRWAD)

This register holds the unique address to be compared with the address contained in the incoming CEIR message. If CEIR

is enabled (bit 0 of the IRWCR register is 1) and an address match occurs, then bit 5 of the WK0_STS register is set to 1

(see Section 3.4.2).

This register is set to 00h on power-up of VPP or software reset.

Location:

Bank 1, Offset 15h

Type:

R/W

3.4.24

CEIR Wake-Up Address Mask Register (IRWAM)

Each bit in this register determines whether the corresponding bit in the IRWAD register is enabled in the address compar-

ison. Bits 5, 6 and 7 must be set to 1 if the RC-5 protocol is selected.

This register is set to E0h on power-up of VPP or software reset.

Location:

Bank 1, Offset 16h

Type:

R/W

Bit

76543210

Name

CEIR Wake-Up Address

Reset

00000000

Bit

76543210

Name

CEIR Wake-Up Address Mask

Reset

11100000

Bit

Description

7-0

CEIR Wake-Up Address Mask. If the corresponding bit is 0, the address bit is not masked (enabled for

compare). If the corresponding bit is 1, the address bit is masked (ignored during compare).

PC87366 数据表(PDF) 107 Page - National Semiconductor (TI)

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