AT89C51ED2-RDTIM datasheet(71/137 Pages) ATMEL

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AT89C51RD2/ED2

4235E–8051–04/04

Reset Value = 0001 0100b

Not bit addressable

Serial Peripheral Status Register

(SPSTA)

The Serial Peripheral Status Register contains flags to signal the following conditions:

•

Data transfer complete

•

Write collision

•

Inconsistent logic level on SS pin (mode fault error)

Table 49 describes the SPSTA register and explains the use of every bit in the register.

Table 49. SPSTA Register

SPSTA - Serial Peripheral Status and Control register (0C4H)

SPR1

SPR2

SPR1

SPR0 Serial Peripheral Rate

CLK PERIPH /2

CLK PERIPH /4

CLK PERIPH /8

CLK PERIPH /16

CLK PERIPH /32

CLK PERIPH /64

CLK PERIPH /128

Invalid

SPR0

Bit Number

Bit Mnemonic

Description

SPIF

WCOL

SSERR

MODF

Bit

Number

Bit

Mnemonic Description

SPIF

Serial Peripheral Data Transfer Flag

Cleared by hardware to indicate data transfer is in progress or has been

approved by a clearing sequence.

Set by hardware to indicate that the data transfer has been completed.

6WCOL

Write Collision Flag

Cleared by hardware to indicate that no collision has occurred or has been

approved by a clearing sequence.

Set by hardware to indicate that a collision has been detected.

SSERR

Synchronous Serial Slave Error Flag

Set by hardware when SS is de-asserted before the end of a received data.

Cleared by disabling the SPI (clearing SPEN bit in SPCON).

4MODF

Mode Fault

Cleared by hardware to indicate that the SS pin is at appropriate logic level, or

has been approved by a clearing sequence.

Set by hardware to indicate that the SS pin is at inappropriate logic level.

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

AT89C51ED2-RDTIM 数据表(PDF) 71 Page - ATMEL Corporation

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