AT89C51ED2-RDTIM datasheet(2/137 Pages) ATMEL

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AT89C51RD2/ED2

4235E–8051–04/04

The AT89C51RD2/ED2 retains all of the features of the Atmel 80C52 with 256 bytes of

internal RAM, a 9-source 4-level interrupt controller and three timer/counters. The

AT89C51ED2 provides 2048 bytes of EEPROM for nonvolatile data storage.

In addition, the AT89C51RD2/ED2 has a Programmable Counter Array, an XRAM of

1792 bytes, a Hardware Watchdog Timer, SPI interface, Keyboard, a more versatile

serial channel that facilitates multiprocessor communication (EUART) and a speed

improvement mechanism (X2 Mode).

The fully static design of the AT89C51RD2/ED2 allows to reduce system power con-

sumption by bringing the clock frequency down to any value, including DC, without loss

of data.

The AT89C51RD2/ED2 has 2 software-selectable modes of reduced activity and an 8-

bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU

is frozen while the peripherals and the interrupt system are still operating. In the Power-

down mode the RAM is saved and all other functions are inoperative.

The added features of the AT89C51RD2/ED2 make it more powerful for applications

that need pulse width modulation, high speed I/O and counting capabilities such as

alarms, motor control, corded phones, and smart card readers.

Table 1. Memory Size and I/O Pins

Package

Flash (Bytes)

XRAM (Bytes)

Total RAM (Bytes)

I/O

PLCC44/VQFP44/DIL40

64K

1792

2048

PLCC68/VQFP64

64K

1792

2048

AT89C51ED2-RDTIM 数据表(PDF) 2 Page - ATMEL Corporation