AT89C51ED2-RDTIM datasheet(26/137 Pages) ATMEL

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AT89C51RD2/ED2

4235E–8051–04/04

Registers

Table 19. AUXR Register

AUXR - Auxiliary Register (8Eh)

Reset Value = 0X00 10’HSB. XRAM’0b

Not bit addressable

DPU

XRS2

XRS1

XRS0

EXTRAM

Bit

Number

Bit

Mnemonic

Description

7DPU

Disable Weak Pull-up

Cleared by software to activate the permanent weak pull-up (default)

Set by software to disable the weak pull-up (reduce power consumption)

Reserved

The value read from this bit is indeterminate. Do not set this bit.

5M0

Pulse length

Cleared to stretch MOVX control: the RD and the WR pulse length is 6 clock

periods (default).

Set to stretch MOVX control: the RD and the WR pulse length is 30 clock periods.

4XRS2

XRAM Size

XRS2

XRS1 XRS0

XRAM size

256 bytes

512 bytes

768 bytes(default)

1024 bytes

1792 bytes

3XRS1

2XRS0

EXTRAM

EXTRAM bit

Cleared to access internal XRAM using movx @ Ri/ @ DPTR.

Set to access external memory.

Programmed by hardware after Power-up regarding Hardware Security Byte

(HSB), default setting, XRAM selected.

0AO

ALE Output bit

Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if

X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC

instruction is used.

AT89C51ED2-RDTIM 数据表(PDF) 26 Page - ATMEL Corporation

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