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AT89C51ED2-RDTIM 数据表(PDF) 78 Page - ATMEL Corporation |
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AT89C51ED2-RDTIM 数据表(HTML) 78 Page - ATMEL Corporation |
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78 / 137 page  78 AT89C51RD2/ED2 4235E–8051–04/04 Table 55. IPH0 Register IPH0 - Interrupt Priority High Register (B7h) Reset Value = X000 0000b Not bit addressable 76 54 32 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6 PPCH PCA interrupt Priority high bit. PPCH PPCL Priority Level 00 Lowest 01 10 1 1 Highest 5PT2H Timer 2 overflow interrupt Priority High bit PT2H PT2L Priority Level 00 Lowest 01 10 1 1 Highest 4 PSH Serial port Priority High bit PSH PSL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest 3PT1H Timer 1 overflow interrupt Priority High bit PT1H PT1L Priority Level 00 Lowest 01 10 1 1 Highest 2 PX1H External interrupt 1 Priority High bit PX1H PX1L Priority Level 00 Lowest 01 10 1 1 Highest 1PT0H Timer 0 overflow interrupt Priority High bit PT0H PT0L Priority Level 00 Lowest 0 1 10 1 1 Highest 0 PX0H External interrupt 0 Priority High bit PX0H PX0L Priority Level 0 0 Lowest 01 10 1 1 Highest |
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