AT89C51ED2-RDTIM datasheet(89/137 Pages) ATMEL

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AT89C51RD2/ED2

4235E–8051–04/04

Power-off Flag

The power-off flag allows the user to distinguish between a “cold start” reset and a

“warm start” reset.

A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while

VCC is still applied to the device and could be generated for example by an exit from

power-down.

The power-off flag (POF) is located in PCON register (Table 64). POF is set by hard-

ware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by

software allowing the user to determine the type of reset.

Table 64. PCON Register

PCON - Power Control Register (87h)

Reset Value = 00X1 0000b

Not bit addressable

SMOD1

SMOD0

POF

GF1

GF0

IDL

Bit

Number

Bit

Mnemonic

Description

7SMOD1

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

6SMOD0

Serial port Mode bit 0

Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4POF

Power-Off Flag

Cleared by software to recognize the next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by

software.

3GF1

General-purpose Flag

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

2GF0

General-purpose Flag

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

1PD

Power-down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

0IDL

Idle mode bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

AT89C51ED2-RDTIM 数据表(PDF) 89 Page - ATMEL Corporation

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