AT89C51ED2-RDTIM datasheet(22/137 Pages) ATMEL

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AT89C51RD2/ED2

4235E–8051–04/04

Table 18. AUXR1 Register

AUXR1- Auxiliary Register 1(0A2h)

Reset Value = XXXX XX0X0b

Not bit addressable

Note:

1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

ASSEMBLY LANGUAGE

; Block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; note:

DPS exits opposite of entry state

; unless an extra INC AUXR1 is added

;

00A2

AUXR1 EQU 0A2H

;

0000 909000MOV DPTR,#SOURCE ; address of SOURCE

0003 05A2 INC AUXR1 ; switch data pointers

0005 90A000 MOV DPTR,#DEST ; address of DEST

0008

LOOP:

0008 05A2 INC AUXR1 ; switch data pointers

000A E0 MOVX A,@DPTR ; get a byte from SOURCE

000B A3 INC DPTR ; increment SOURCE address

000C 05A2 INC AUXR1 ; switch data pointers

000E F0 MOVX @DPTR,A ; write the byte to DEST

000F A3 INC DPTR ; increment DEST address

0010 70F6JNZ LOOP ; check for 0 terminator

0012 05A2 INC AUXR1 ; (optional) restore DPS

ENBOOT

GF3

DPS

Bit

Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

ENBOOT

Enable Boot Flash

Cleared to disable boot ROM.

Set to map the boot ROM between F800h - 0FFFFh.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3GF3

This bit is a general-purpose user flag.(1)

Always cleared

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0DPS

Data Pointer Selection

Cleared to select DPTR0.

Set to select DPTR1.

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