AT89C51ED2-RDTIM datasheet(15/137 Pages) ATMEL

15 / 137 page

AT89C51RD2/ED2

4235E–8051–04/04

Oscillator

To optimize the power consumption and execution time needed for a specific task, an

internal prescaler feature has been implemented between the oscillator and the CPU

and peripherals.

Registers

Table 14. CKRL Register

CKRL – Clock Reload Register (97h)

Reset Value = 1111 1111b

Not bit addressable

Table 15. PCON Register

PCON – Power Control Register (87h)

Reset Value = 00X1 0000b Not bit addressable

765

CKRL7

CKRL6

CKRL5

CKRL4

CKRL3

CKRL2

CKRL1

CKRL0

Bit Number

Mnemonic

Description

7:0

CKRL

Clock Reload Register

Prescaler value

SMOD1

SMOD0

POF

GF1

GF0

IDL

Bit Number

Bit Mnemonic

Description

7SMOD1

Serial Port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

6SMOD0

Serial Port Mode bit 0

Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4POF

Power-off Flag

Cleared by software to recognize the next reset type.

Set by hardware when V

CC rises from 0 to its nominal voltage. Can

also be set by software.

3GF1

General-purpose Flag

Cleared by software for general-purpose usage.

Set by software for general-purpose usage.

2GF0

General-purpose Flag

Cleared by software for general-purpose usage.

Set by software for general-purpose usage.

1PD

Power-down Mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

0IDL

Idle Mode bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

AT89C51ED2-RDTIM 数据表(PDF) 15 Page - ATMEL Corporation

AT89C51ED2-RDTIM 数据表(HTML) 15 Page - ATMEL Corporation

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