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AT89C51ED2-RDTIM 数据表(PDF) 16 Page - ATMEL Corporation |
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AT89C51ED2-RDTIM 数据表(HTML) 16 Page - ATMEL Corporation |
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16 / 137 page  16 AT89C51RD2/ED2 4235E–8051–04/04 Functional Block Diagram Figure 4. Functional Oscillator Block Diagram Prescaler Divider • A hardware RESET puts the prescaler divider in the following state: •CKRL = FFh: FCLK CPU = FCLK PERIPH = FOSC/2 (Standard C51 feature) • Any value between FFh down to 00h can be written by software into CKRL register in order to divide frequency of the selected oscillator: • CKRL = 00h: minimum frequency FCLK CPU = FCLK PERIPH = FOSC/1020 (Standard Mode) FCLK CPU = FCLK PERIPH = FOSC/510 (X2 Mode) • CKRL = FFh: maximum frequency F CLK CPU = FCLK PERIPH = FOSC/2 (Standard Mode) F CLK CPU = FCLK PERIPH = FOSC (X2 Mode) F CLK CPU and FCLK PERIPH In X2 Mode, for CKRL<>0xFF: In X1 Mode, for CKRL<>0xFF then: Xtal2 Xtal1 Osc CLK Idle CPU Clock CKRL Reload 8-bit Prescaler-Divider Reset Peripheral Clock :2 X2 0 1 FOSC CKCON0 CLK Periph CPU CKRL = 0xFF? 0 1 F CPU F = CLKPER IPH F OSC 2 255 CKRL – () × ----------------------------------------------- = F CPU F = CLKPER IPH F OSC 4 255 CKRL – () × ----------------------------------------------- = |
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