AT89C51ED2-RDTIM datasheet(91/137 Pages) ATMEL

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AT89C51RD2/ED2

4235E–8051–04/04

EEPROM Data

Memory

This feature is available only for the AT89C51ED2 device.

The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh

of the XRAM/ERAM memory space and is selected by setting control bits in the EECON

A read or write access to the EEPROM memory is done with a MOVX instruction.

Write Data

Data is written by byte to the EEPROM memory block as for an external RAM memory.

The following procedure is used to write to the EEPROM memory:

•

Check EEBUSY flag

•

If the user application interrupts routines use XRAM memory space: Save and

disable interrupts.

•

Load DPTR with the address to write

•

Store A register with the data to be written

•

Set bit EEE of EECON register

•

Execute a MOVX @DPTR, A

•

Clear bit EEE of EECON register

•

Restore interrupts.

•

EEBUSY flag in EECON is then set by hardware to indicate that programming is in

progress and that the EEPROM segment is not available for reading or writing.

•

The end of programming is indicated by a hardware clear of the EEBUSY flag.

Figure 38 represents the optimal write sequence to the on-chip EEPROM data memory.

AT89C51ED2-RDTIM 数据表(PDF) 91 Page - ATMEL Corporation