AT89C51ED2-RDTIM datasheet(34/137 Pages) ATMEL

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AT89C51RD2/ED2

4235E–8051–04/04

Registers

Table 20. T2CON Register

T2CON - Timer 2 Control Register (C8h)

Reset Value = 0000 0000b

Bit addressable

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number

Bit

Mnemonic

Description

TF2

Timer 2 overflow Flag

Must be cleared by software.

Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0.

6EXF2

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2 = 1.

When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2

interrupt is enabled.

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down

counter mode (DCEN = 1).

RCLK

Receive Clock bit

Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

4TCLK

Transmit Clock bit

Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

EXEN2

Timer 2 External Enable bit

Cleared to ignore events on T2EX pin for Timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is

detected, if Timer 2 is not used to clock the serial port.

2TR2

Timer 2 Run control bit

Cleared to turn off Timer 2.

Set to turn on Timer 2.

1C/T2#

Timer/Counter 2 select bit

Cleared for timer operation (input from internal clock system: FCLK PERIPH).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0

for clock out mode.

0CP/RL2#

Timer 2 Capture/Reload bit

If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload

on Timer 2 overflow.

Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin

if EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2 = 1.

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