AT89C51ED2-RDTIM datasheet(45/137 Pages) ATMEL

45 / 137 page

AT89C51RD2/ED2

4235E–8051–04/04

Figure 19. PCA Compare Mode and PCA Watchdog Timer

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value,

otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit.

Once ECOM is set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t

occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this

reason, user software should write CCAPnL first, and then CCAPnH. Of course, the

ECOM bit can still be controlled by accessing to CCAPMn register.

High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle

each time a match occurs between the PCA counter and the modules capture registers.

To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR

must be set (See Figure 20).

A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.

CCAPnH

CCAPnL

ECOMn

CCAPMn, n = 0 to 4

0xDA t o 0xDE

CAPNn MATn TOGn PWMn ECCFn

CAPPn

16 bit comparator

Match

CCON

0xD8

PCA I T

Enable

PCA counter/ timer

RESET *

CIDL

CPS1 CPS0

ECF

CMOD

0xD9

WDTE

Reset

Write to

CCAPnL

Write to

CCAPnH

CCF2 CCF1

CCF0

CCF3

CCF4

AT89C51ED2-RDTIM 数据表(PDF) 45 Page - ATMEL Corporation

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