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AT89C51ED2-RDTIM 数据表(PDF) 24 Page - ATMEL Corporation |
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AT89C51ED2-RDTIM 数据表(HTML) 24 Page - ATMEL Corporation |
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24 / 137 page ![]() 24 AT89C51RD2/ED2 4235E–8051–04/04 Expanded RAM (XRAM) The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM) space for increased data parameter handling and high level language usage. AT89C51RD2/ED2 device haS expanded RAM in external data space configurable up to 1792 bytes (see Table 19). The AT89C51RD2/ED2 internal data memory is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable. 2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only. 3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly addressable only. 4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register (see Table 19). The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. Figure 8. Internal and External Data Memory Address When an instruction accesses an internal location above address 7Fh, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. • Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data, accesses the SFR at location 0A0h (which is P2). • Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address 0A0h, rather than P2 (whose address is 0A0h). • The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table 19. This can be XRAM Upper 128 Bytes Internal RAM Lower 128 Bytes Internal RAM Special Function Register 80h 80h 00 0FFh or 6FFh 0FFh 00 0FFh External Data Memory 0000 00FFh up to 06FFh 0FFFFh Indirect Accesses Direct Accesses Direct or Indirect Accesses 7Fh |
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