AT89C51ED2-RDTIM datasheet(85/137 Pages) ATMEL

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AT89C51RD2/ED2

4235E–8051–04/04

Registers

Table 60. PCON Register

PCON (S87:h) Power configuration Register

Reset Value= XXXX 0000b

GF1

GF0

IDL

Bit

Number

Bit

Mnemonic

Description

7-4

Reserved

The value read from these bits is indeterminate. Do not set these bits.

3GF1

General Purpose flag 1

One use is to indicate whether an interrupt occurred during normal operation or

during Idle mode.

2GF0

General Purpose flag 0

One use is to indicate whether an interrupt occurred during normal operation or

during Idle mode.

1PD

Power-Down Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-Down mode.

If IDL and PD are both set, PD takes precedence.

0IDL

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

If IDL and PD are both set, PD takes precedence.

AT89C51ED2-RDTIM 数据表(PDF) 85 Page - ATMEL Corporation

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