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AT89C51ED2-RDTIM 数据表(PDF) 20 Page - ATMEL Corporation |
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AT89C51ED2-RDTIM 数据表(HTML) 20 Page - ATMEL Corporation |
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20 / 137 page ![]() 20 AT89C51RD2/ED2 4235E–8051–04/04 Table 17. CKCON1 Register CKCON1 - Clock Control Register (AFh) Reset Value = XXXX XXX0b Not bit addressable 76 54 32 1 0 -- --- -- SPIX2 Bit Number Bit Mnemonic Description 7- Reserved 6- Reserved 5- Reserved 4- Reserved 3- Reserved 2- Reserved 1- Reserved 0SPIX2 SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. |
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