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AT89C51ED2-RDTIM 数据表(PDF) 81 Page - ATMEL Corporation |
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AT89C51ED2-RDTIM 数据表(HTML) 81 Page - ATMEL Corporation |
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81 / 137 page  81 AT89C51RD2/ED2 4235E–8051–04/04 Table 58. IPH1 Register IPH1 - Interrupt Priority High Register (B3h) Reset Value = XXXX X000b Not bit addressable 76 54 32 1 0 - - - - - SPIH - KBDH Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2SPIH SPI interrupt Priority High bit SPIH SPIL Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest 1- Reserved The value read from this bit is indeterminate. Do not set this bit. 0 KBDH Keyboard interrupt Priority High bit KB DH KBDL Priority Level 00 Lowest 0 1 10 1 1 Highest |
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