AT89C51ED2-RDTIM datasheet(58/137 Pages) ATMEL

58 / 137 page

AT89C51RD2/ED2

4235E–8051–04/04

Table 41. PCON Register

PCON - Power Control Register (87h)

Reset Value = 00X1 0000b

Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset

doesn’t affect the value of this bit.

SMOD1

SMOD0

POF

GF1

GF0

IDL

Bit

Number

Bit

Mnemonic

Description

7SMOD1

Serial port Mode bit 1 for UART

Set to select double baud rate in mode 1, 2 or 3.

6SMOD0

Serial port Mode bit 0 for UART

Cleared to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4POF

Power-Off Flag

Cleared to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set

by software.

3GF1

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

2GF0

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

1PD

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

0IDL

Idle mode bit

Cleared by hardware when interrupt or reset occurs.

Set to enter idle mode.

AT89C51ED2-RDTIM 数据表(PDF) 58 Page - ATMEL Corporation

AT89C51ED2-RDTIM 数据表(HTML) 58 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载