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AT89C51ED2-RDTIM 数据表(PDF) 98 Page - ATMEL Corporation |
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AT89C51ED2-RDTIM 数据表(HTML) 98 Page - ATMEL Corporation |
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98 / 137 page  98 AT89C51RD2/ED2 4235E–8051–04/04 Table 69. Default Values After programming the part by ISP, the BSB must be cleared (00h) in order to allow the application to boot at 0000h. The content of the Software Security Byte (SSB) is described in Table 70 and Table 71. To assure code protection from a parallel access, the HSB must also be at the required level. Table 70. Software Security Byte The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown in Table 71. Mnemonic Definition Default value Description SBV Software Boot Vector FCh BSB Boot Status Byte 0FFh SSB Software Security Byte FFh Copy of the Manufacturer Code 58h Atmel Copy of the Device ID #1: Family Code D7h C51 X2, Electrically Erasable Copy of the Device ID #2: Memories Size and Type ECh AT89C51RD2/ED2 64KB Copy of the Device ID #3: Name and Revision EFh AT89C51RD2/ED2 64KB, Revision 0 76 54 32 1 0 -- --- - LB1 LB0 Bit Number Bit Mnemonic Description 7- Reserved Do not clear this bit. 6- Reserved Do not clear this bit. 5- Reserved Do not clear this bit. 4- Reserved Do not clear this bit. 3- Reserved Do not clear this bit. 2- Reserved Do not clear this bit. 1-0 LB1-0 User Memory Lock Bits See Table 71 |
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