STM8S datasheet(189/467 Pages) STMICROELECTRONICS

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RM0016

16-bit advanced control timer (TIM1)

261

Bit 2 URS: Update request source

0: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent when one

of the following events occurs:

–

Registers are updated (counter overflow/underflow)

–

UG bit is set by software

–

Update event is generated through the clock/trigger controller

1: When enabled by the UDIS bit, the UIF bit is set and an update interrupt request is sent only when

registers are updated (counter overflow/underflow).

Bit 1 UDIS: Update disable.

0: A UEV is generated as soon as a counter overflow occurs, a software update is generated, or a

hardware reset is generated by the clock/trigger mode controller. Buffered registers are then loaded

with their preload values.

1: A UEV is not generated and shadow registers keep their value (ARR, PSC, CCRi). The counter

and the prescaler are re-initialized if the UG bit is set or if a hardware reset is received from the

clock/trigger mode controller.

Bit 0 CEN: Counter enable

0: Counter disabled

1: Counter enabled

Note: External clock, trigger gated mode, and encoder mode can work only if the CEN bit has been

previously set by software. However, trigger mode can set the CEN bit automatically by

hardware.

STM8S 数据表(PDF) 189 Page - STMicroelectronics