STM8S datasheet(193/467 Pages) STMICROELECTRONICS

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RM0016

16-bit advanced control timer (TIM1)

261

Bit 6 ECE: External clock enable

This bit enables external clock mode 2.

0: External clock mode 2 disabled

1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal.

Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI

connected to ETRF (SMS = 111 and TS = 111 in the TIM1_SMCR register).

It is possible to simultaneously use external clock mode 2 with the following modes: Trigger

standard mode, trigger reset mode, and trigger gated mode. Nevertheless, TRGI must not be

connected to ETRF in these cases (TS bits must not be 111 in the TIM1_SMCR register).

If external clock mode 1 and external clock mode 2 are enabled at the same time, the external

clock input is ETRF.

Bits 5:4 ETPS: External trigger prescaler

The ETRP frequency must be, at most,1/4 of fMASTER frequency. A prescaler can be enabled to

reduce ETRP frequency. It is useful when inputting fast external clocks.

00: Prescaler off

01: ETRP frequency divided by 2

10: ETRP frequency divided by 4

11: ETRP frequency divided by 8

Bits 3:0 ETF: External trigger filter.

This bitfield defines the frequency used to sample the ETRP signal and the length of the digital filter

applied to it. The digital filter is made of an event counter in which N events are needed to validate a

transition on the output:

0000: No filter, sampling is done at fMASTER

0001: fSAMPLING=fMASTER, N = 2

0010: fSAMPLING=fMASTER, N = 4

0011: fSAMPLING=fMASTER, N = 8

0100: fSAMPLING=fMASTER/2, N = 6

0101: fSAMPLING=fMASTER/2, N = 8

0110: fSAMPLING=fMASTER/4, N = 6

0111: fSAMPLING=fMASTER/4, N = 8

1000: fSAMPLING=fMASTER/8, N = 6

1001: fSAMPLING=fMASTER/8, N = 8

1010: fSAMPLING=fMASTER/16, N = 5

1011: fSAMPLING=fMASTER/16, N = 6

1100: fSAMPLING=fMASTER/16, N = 8

1101: fSAMPLING=fMASTER/32, N = 5

1110: fSAMPLING=fMASTER/32, N = 6

1111: fSAMPLING=fMASTER/32, N = 8

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