ZUSBOPTSC01ZAC datasheet(141/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

Multiprocessor Mode

Z8FMC16100 Series Flash MCU

Product Specification

119

In Multiprocessor (9-bit) mode, the Parity bit location (9th bit) becomes the MULTIPRO-

CESSOR control bit. The LIN-UART Control 1 and Status 1 registers provide MULTI-

PROCESSOR (9-bit) mode control and status information. If an automatic address

matching scheme is enabled, the LIN-UART Address Compare register holds the network

address of the device.

Multiprocessor Mode Receive Interrupts

When MULTIPROCESSOR (9-bit) mode is enabled, the LIN-UART processes only

frames addressed to it. The determination of whether a frame of data is addressed to the

LIN-UART can be made in hardware, software or a combination of the two, depending on

the multiprocessor configuration bits. In general, the address compare feature reduces the

load on the CPU, because it does not need to access the LIN-UART when it receives data

directed to other devices on the multinode network. The following three MULTIPROCES-

SOR modes are available in hardware:

• Interrupt on all address bytes

• Interrupt on matched address bytes and correctly framed data bytes

• Interrupt only on correctly framed data bytes

These modes are selected with MPMD[1:0] in the LIN-UART Control 1 Register. For all

multiprocessor modes, bit MPEN of the LIN-UART Control 1 Register must be set to 1.

The first scheme is enabled by writing 01b to MPMD[1:0]. In this mode, all incoming

address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt

service routine checks the address byte that triggered the interrupt. If it matches the LIN-

UART address, the software clears MPMD[0]. At this point, each new incoming byte

interrupts the CPU. The software determines the end of the frame and checks for it by

reading the MPRX bit of the LIN-UART Status 1 Register for each incoming byte. If

MPRX

=1, a new frame has begun. If the address of this new frame is different from the

LIN-UART’s address, then MPMD[0] must be set to 1 by software, causing the LIN-

UART interrupts to go inactive until the next address byte. If the new frame’s address

matches the LIN-UART’s, then the data in the new frame is processed as well.

Figure 15. LIN-UART Asynchronous Multiprocessor Mode Data Format

Data Field

Start

Idle State

of Line

Stop Bit(s)

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

lsb

msb

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