ZUSBOPTSC01ZAC datasheet(142/402 Pages) ZILOG

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LIN-UART

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

120

The second scheme is enabled by setting MPMD[1:0] to 10B and writing the LIN-UART’s

address into the LIN-UART Address Compare Register. This mode introduces more hard-

ware control, interrupting only on frames that match the LIN-UART’s address. When an

incoming address byte does not match the LIN-UART’s address, it is ignored. All succes-

sive data bytes in this frame are also ignored. When a matching address byte occurs, an

interrupt is issued and further interrupts occur on each successive data byte. The first data

byte in the frame has NEWFRM=1 in the LIN-UART Status 1 Register. When the next

address byte occurs, the hardware compares it to the LIN-UART’s address. If there is a

match, the interrupt occurs and the NEWFRM bit is set for the first byte of the new frame. If

there is no match, the LIN-UART ignores all incoming bytes until the next address match.

The third scheme is enabled by setting MPMD[1:0] to 11B and by writing the LIN-UART’s

address into the LIN-UART Address Compare Register. This mode is identical to the sec-

ond scheme, except that there are no interrupts on address bytes. The first data byte of

each frame remains accompanied by a NEWFRM assertion.

LIN Protocol Mode

The LIN (Local Interconnect Network) protocol as supported by the LIN-UART module is

defined in rev 2.0 of the LIN Specification Package. The LIN protocol specification cov-

ers all aspects of transferring information between LIN Master and Slave devices using

message frames including error detection and recovery, sleep mode and wake up from

sleep mode. The LIN-UART hardware in LIN mode provides character transfers to sup-

port the LIN protocol including BREAK transmission and detection, WAKE-UP transmis-

sion and detection, and slave autobauding. Part of the error detection of the LIN protocol

is for both master and slave devices to monitor their receive data when transmitting. If the

receive and transmit data streams do not match, the LIN-UART asserts the PLE bit (phys-

ical layer error bit in Status0 register). The message frame time-out aspect of the protocol

is left to software, requiring the use of an additional general purpose timer. The LIN mode

of the LIN-UART does not provide any hardware support for computing/verifying the

checksum field or verifying the contents of the Identifier field. These fields are treated as

data and are not interpreted by hardware. The checksum calculation/verification can easily

be implemented in software via the ADC (Add with Carry) instruction.

The LIN bus contains a single master and one or more slaves. The LIN master is responsi-

ble for transmitting the message frame header which consists of the Break, Synch and

Identifier fields. Either the master or one of the slaves transmits the associated response

section of the message which consists of data characters followed by a checksum charac-

ter.

In LIN mode, the interrupts defined for normal UART operation still apply with the fol-

lowing changes.

• Parity Error (PE bit in Status0 register) is redefined as the Physical Layer Error (PLE)

bit. The PLE bit indicates that receive data does not match transmit data when the LIN-

UART is transmitting. This applies to both Master and Slave operating modes.

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