ZUSBOPTSC01ZAC datasheet(146/402 Pages) ZILOG

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LIN-UART

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

124

If the Identifier character indicates that this slave device is not participating in the mes-

sage, software can set the LinState[1:0] = 01b (Wait for Break State) to ignore the rest

of the message. No further receive interrupts will occur until the next Break.

LIN-UART Interrupts

The LIN-UART features separate interrupts for the transmitter and receiver. In addition,

when the LIN-UART primary functionality is disabled, the Baud Rate Generator can also

function as a basic timer with interrupt capability.

Transmitter Interrupts

The transmitter generates a single interrupt when the Transmit Data Register Empty bit

(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-

mission. The TDRE interrupt occurs when the transmitter is initially enabled and after the

Transmit shift register has shifted the first bit of a character out. At this point, the Transmit

Data Register may be written with the next character to send. This provides 7 bit periods

of latency to load the Transmit Data Register before the Transmit shift register completes

shifting the current character. Writing to the LIN-UART Transmit Data Register clears the

TDRE

bit to 0.

Receiver Interrupts

The receiver generates an interrupt when any of the following occurs:

• A data byte has been received and is available in the LIN-UART Receive Data Regis-

ter. This interrupt can be disabled independent of the other receiver interrupt sources

via the RDAIRQ bit (this feature is useful in devices which support DMA). The received

data interrupt occurs once the receive character has been placed in the Receive Data

next character is completely received to avoid an overrun error.

In MULTIPROCESSOR mode (MPEN = 1), the receive data interrupts are dependent on

the multiprocessor configuration and the most recent address byte

• A break is received

• A receive data overrun or LIN slave autobaud overrun error is detected.

• A data framing error is detected

• A parity error is detected (physical layer error in LIN mode)

LIN-UART Overrun Errors

When an overrun error condition occurs the LIN-UART prevents overwriting of the valid

data currently in the Receive Data Register. The Break Detect and Overrun status bits are

not displayed until after the valid data has been read.

Note:

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