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ZUSBOPTSC01ZAC 数据表(PDF) 149 Page - Zilog, Inc. |
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ZUSBOPTSC01ZAC 数据表(HTML) 149 Page - Zilog, Inc. |
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149 / 402 page ![]() PS024604-1005 P R E L I M I N A R Y LIN-UART Baud Rate Generator Z8FMC16100 Series Flash MCU Product Specification 127 The transmitter can be enabled in this mode. LIN-UART Baud Rate Generator The LIN-UART Baud Rate Generator creates a lower frequency baud rate clock for data transmission. The input to the Baud Rate Generator is the system clock. The LIN-UART Baud Rate High and Low Byte registers combine to create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate (baud rate) of the LIN-UART. The LIN- UART data rate is calculated using the following equation for normal UART operation: The LIN-UART data rate is calculated using the following equation for LIN mode UART operation: When the LIN-UART is disabled, the Baud Rate Generator can function as a basic 16-bit timer with interrupt on time-out. To configure the Baud Rate Generator as a timer with interrupt on time-out, complete the following procedure: 1. Disable the LIN-UART receiver by clearing the REN bit in the LIN-UART Control 0 Register to 0 (TEN bit may be asserted, transmit activity may occur). 2. Load the appropriate 16-bit count value into the LIN-UART Baud Rate High and Low Byte registers. 3. Enable the Baud Rate Generator timer function and associated interrupt by setting the BRGCTL bit in the LIN-UART Control 1 Register to 1. Noise Filter A noise filter circuit is included which filters noise on a digital input signal (such as UART Receive Data) before the data is sampled by the block. This is likely to be a requirement for protocols with a noisy environment. The noise filter contains the following features: • Synchronizes the receive input data to the System Clock • Noise Filter Enable (NFEN) input selects whether the noise filter is bypassed (NFEN = 0) or included (NFEN = 1) in the receive data path. UART Data Rate (bits/s) = System Clock Frequency (Hz) 16 x UART Baud Rate Divisor Value UART Data Rate (bits/s) = System Clock Frequency (Hz) UART Baud Rate Divisor Value |
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