ZUSBOPTSC01ZAC datasheet(147/402 Pages) ZILOG

147 / 402 page

PS024604-1005

P R E L I M I N A R Y

LIN-UART Interrupts

Z8FMC16100 Series Flash MCU

Product Specification

125

After the valid data has been read, the OE bit of the Status 0 register is updated to indicate

the overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate

that the Receive Data Register contains a data byte. However, because the overrun error

occurred, this byte may not contain valid data and must be ignored. The BRKD bit indicates

if the overrun was caused by a break condition on the line. After reading the status byte

indicating an overrun error, the Receive Data Register must be read again to clear the error

bits in the LIN-UART Status 0 register.

In LIN mode, an Overrun Error is signaled for receive data overruns as described above

and in the LIN Slave if the BRG Counter overflows during the autobaud sequence (the

ATB

bit will also be set in this case). There is no data associated with the autobaud over-

flow interrupt, however the Receive Data Register must be read to clear the OE bit. In this

case software must write a 10B to the LinState field, forcing the LIN slave back to a

Wait for Break state.

LIN-UART Data- and Error-Handling Procedure

Figure 16 illustrates the recommended procedure for use in LIN-UART receiver interrupt

service routines.

ZUSBOPTSC01ZAC 数据表(PDF) 147 Page - Zilog, Inc.