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ZUSBOPTSC01ZAC 数据表(PDF) 153 Page - Zilog, Inc.

部件名 ZUSBOPTSC01ZAC
功能描述  Z8 Encore-R Motor Control Flash MCUs
PDF  402 Pages
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制造商  ZILOG [Zilog, Inc.]
网页  http://www.zilog.com
标志 ZILOG - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 153 Page - Zilog, Inc.

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PS024604-1005
P R E L I M I N A R Y
LIN-UART Status 0 Register
Z8FMC16100 Series Flash MCU
Product Specification
131
RXD—Receive Data
LIN-UART receiver data byte from the RXD pin
LIN-UART Status 0 Register
The LIN-UART Status 0 Register identifies the current LIN-UART operating configura-
tion and status. Table 68 describes the Status 0 Register for standard UART mode. Table
69, which follows on page 132, describes the Status0 Register for LIN mode. A more
detailed discussion of each bit follows each table.
Receive Data Available (RDA).
This bit indicates that the LIN-UART Receive Data Reg-
ister has received data. Reading the LIN-UART Receive Data Register clears this bit.
Parity Error (PE).
This bit indicates that a parity error has occurred. Reading the Receive
Data Register clears this bit.
Overrun Error (OE).
This bit indicates that an overrun error has occurred. An overrun
occurs when new data is received and the Receive Data Register has not been read. Read-
ing the Receive Data Register clears this bit.
Framing Error (FE).
This bit indicates that a framing error (no STOP bit following data
reception) was detected. Reading the Receive Data Register clears this bit.
Break Detect (BRKD).
This bit indicates that a break occurred. If the data bits, parity/
multiprocessor bit, and STOP bit(s) are all zeros then this bit is set to 1. Reading the
Receive Data Register clears this bit.
Transmitter Data Register Empty (TDRE).
This bit indicates that the Transmit Data
Register is empty and ready for additional data. Writing to the Transmit Data Register
resets this bit.
Transmitter Empty (TXE).
This bit indicates that the transmit shift register is empty and
character transmission is finished.
Clear To Send Signal (CTS).
When this bit is read it returns the level of the CTS signal.
If LBEN = 1, the CTS input signal is replaced by the internal Receive Data Available sig-
Table 68. LIN-UART Status 0 Register - standard UART mode (U0STAT0)
BITS
7
6
5
4
3
2
1
0
FIELD
RDA
PE
OE
FE
BRKD
TDRE
TXE
CTS
RESET
00
00
0
1
1
X
R/W
RR
RR
R
R
R
R
ADDR
F41H



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