ZUSBOPTSC01ZAC datasheet(157/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

LIN-UART Control 0 Register

Z8FMC16100 Series Flash MCU

Product Specification

135

TEN—Transmit Enable

This bit enables or disables the transmitter. The enable is also controlled by the CTS signal

and the CTSE bit. If the CTS signal is Low and the CTSE bit is 1, the transmitter is

enabled.

0 = Transmitter disabled.

1 = Transmitter enabled.

REN—Receive Enable

This bit enables or disables the receiver.

0 = Receiver disabled.

1 = Receiver enabled.

CTSE—CTS Enable

0 = The CTS signal has no effect on the transmitter.

1 = The LIN-UART recognizes the CTS signal as an enable control for the transmitter.

PEN—Parity Enable

This bit enables or disables parity. Even or odd is determined by the PSEL bit.

0 = Parity is disabled. This bit is overridden by the MPEN bit.

1 = The transmitter sends data with an additional parity bit and the receiver receives an

additional parity bit.

PSEL—Parity Select

0 = Even parity is transmitted and expected on all received data.

1 = Odd parity is transmitted and expected on all received data.

SBRK—Send Break

This bit pauses or breaks data transmission. Sending a break interrupts any transmission in

progress, so ensure that the transmitter has finished sending data before setting this bit. In

standard UART mode, the duration of the break is determined by how long software

leaves this bit asserted. Also the duration of any required Stop bits following the break

must be timed by software before writing a new byte to be transmitted to the transmit data

of the break is timed by hardware, and the SBRK bit is deasserted by hardware when the

Break is completed. The duration of the Break is determined by the TxBreakLength field

Table 71. LIN-UART Control 0 Register (U0CTL0)

BITS

FIELD

TEN

REN

CTSE

PEN

PSEL

SBRK

STOP

LBEN

RESET

000

R/W

R/WR/W

ADDR

F42H

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