ZUSBOPTSC01ZAC datasheet(160/402 Pages) ZILOG

160 / 402 page

LIN-UART

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

138

Noise Filter Control Register

When MSEL = 001b, the Noise Filter Control Register, shown in Table , provides control

for the digital noise filter. A more detailed discussion of each bit follows the table.

NFEN—Noise Filter Enable

0 = Noise filter is disabled.

1 = Noise filter is enabled. Receive data is preprocessed by the noise filter.

NFCTL—Noise Filter Control

This field controls the delay and noise rejection characteristics of the noise filter. The

wider the counter the more delay that is introduced by the filter and the wider the noise

event that is filtered.

000 = 4-bit up/down counter

001 = 5-bit up/down counter

010 = 6-bit up/down counter

011 = 7-bit up/down counter

100 = 8-bit up/down counter

101 = 9-bit up/down counter

110 = 10-bit up/down counter

111 = 11-bit up/down counter

LIN Control Register

When MSEL = 010b, the LIN Control Register provides control for the LIN mode of oper-

ation. A more detailed discussion of each bit follows the table.

Table 73. Noise Filter Control Register (U0CTL1 with MSEL = 001b)

BITS

FIELD

NFEN

NFCTL

Reserved

RESET

R/W

ADDR

F43H with MSEL = 001b

ZUSBOPTSC01ZAC 数据表(PDF) 160 Page - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 160 Page - Zilog, Inc.

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