ZUSBOPTSC01ZAC datasheet(175/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

SPI Clock Phase and Polarity Control

Z8FMC16100 Series Flash MCU

Product Specification

153

Transfer Format Phase Equals Zero

Figure 25 illustrates the timing diagram for an SPI transfer in which PHASE is cleared to 0.

The two SCK waveforms show polarity with CLKPOL reset to 0 and with CLKPOL set to

1. The diagram can be interpreted as either a master or slave timing diagram because the

SCK Master-In/Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly con-

nected between the master and the slave.

Table 83. SPI Clock Phase and Clock Polarity Operation

PHASE

CLKPOL

SCK Transmit

Edge

SCK Receive

Edge

SCK Idle

State

Falling

Rising

Low

Rising

Falling

High

Rising

Falling

Low

Falling

Rising

High

Figure 25. SPI Timing When Phase is 0

MOSI

SCK

(CLKPOL = 1)

SCK

(CLKPOL = 0)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MISO

Input Sample Time

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

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