ZUSBOPTSC01ZAC datasheet(174/402 Pages) ZILOG

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Serial Peripheral Interface

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

152

Serial Clock

The Serial Clock (SCK) synchronizes data movement both in and out of the device

through its MOSI and MISO pins. In MASTER mode, the SPI’s Baud Rate Generator cre-

ates the serial clock. The master drives the serial clock through its own serial clock (SCK)

pin to the slave’s SCK pin. When the SPI is configured as a slave, the SCK pin is an input

and the clock signal from the master synchronizes the data transfer between the master and

slave devices. These slave devices ignore the SCK signal unless the SS pin is asserted.

When configured as a slave, the SPI block requires a minimum SCK period of greater than

or equal to 8 times the system (XIN) clock period.

The master and slave are each capable of exchanging a character of data during a sequence

of NUMBITS clock cycles (refer to the NUMBITS field in the SPIMODE Register). In both

master and slave SPI devices, data is shifted on one edge of the SCK and is sampled on the

opposite edge, where data is stable. Edge polarity is determined by the SPI phase and

polarity control.

Slave Select

The active Low Slave Select (SS) input signal selects a slave SPI device. SS must be Low

prior to all data communication to and from the slave device. SS must remain Low for the

full duration of each character transferred. The SS signal may stay Low during the transfer

of multiple characters, or may deassert between each character.

When the SPI is configured as the only master in an SPI system, the SS pin can be set as

either an input or an output. For communication between the Z8 Encore!® 8K Series

device’s SPI master and external slave devices, the SS signal, as an output, can assert the

SS input pin on one of the slave devices. Other GPIO output pins can also be employed to

select external SPI slave devices.

When the SPI is configured as one master in a multimaster SPI system, the SS pin should

be set as an input. The SS input signal on the master must be High. If the SS signal goes

Low (indicating that another master is driving the SPI bus), a collision error flag is set in

the SPI Status Register.

SPI Clock Phase and Polarity Control

The SPI supports four combinations of serial clock phase and polarity using two bits in the

SPI Control Register. The clock polarity bit, CLKPOL, selects an active High or active

Low clock and has no effect on the transfer format. Table 83 lists the SPI Clock Phase and

Polarity Operation parameters. The clock phase bit, PHASE, selects one of two fundamen-

tally different transfer formats. For proper data transmission, clock phase and polarity

must be identical for the SPI master and the SPI slave. The master always places data on

the MOSI line a half-cycle before the receive clock edge (SCK signal) for the slave to

latch the data.

ZUSBOPTSC01ZAC 数据表(PDF) 174 Page - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 174 Page - Zilog, Inc.

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