ZUSBOPTSC01ZAC datasheet(177/402 Pages) ZILOG

177 / 402 page

PS024604-1005

P R E L I M I N A R Y

Slave Operation

Z8FMC16100 Series Flash MCU

Product Specification

155

Slave Operation

The SPI block is configured for SLAVE mode operation by setting the SPIEN bit to 1 and

the MMEN bit to 0 in the SPICTL Register and setting the SSIO bit to 0 in the SPIMODE

BITS

field in the SPIMODE Register must be set to be consistent with the other SPI

devices. The STR bit in the SPICTL Register can be used, if appropriate, to force a start-

up interrupt. The BIRQ bit in the SPICTL Register and the SSV bit in the SPIMODE Reg-

ister are not used in SLAVE mode. The SPI baud rate generator is not used in SLAVE

mode; therefore, the SPIBRH and SPIBRL registers do not require initialization.

If the slave contains data to send to the master, the data should be written to the SPIDAT

DAT Register is not written prior to the slave transaction, the MISO pin outputs the value

that is currently in the SPIDAT Register.

Due to the delay resulting from synchronization of the SPI input signals to the internal sys-

tem clock, the maximum SPICLK baud rate that can be supported in SLAVE mode is the

system clock frequency (XIN) divided by 8. This rate is controlled by the SPI master.

Error Detection

The SPI contains error detection logic that supports SPI communication protocols and rec-

ognizes when communication errors have occurred. The SPI Status Register indicates

when a data transmission error has been detected.

Overrun

An overrun error (write collision) indicates that a Write to the SPI Data Register was

attempted while a data transfer is in progress (in either MASTER or SLAVE modes). An

overrun sets the OVR bit in the SPI Status Register to 1. Writing a 1 to OVR clears this

error flag. The SPI Data Register is not altered when a Write occurs while a data transfer is

in progress.

Mode Fault

A mode fault indicates when more than one master is trying to communicate at the same

time (a multimaster collision). The mode fault is detected when the enabled master’s SS

pin is asserted. A mode fault sets the COL bit in the SPI Status Register to 1. Writing a 1 to

COL

clears this error flag.

Slave Mode Abort

In SLAVE mode, if the SS pin deasserts before all bits in a character have been trans-

ferred, the transaction aborts. When this condition occurs, the ABT bit is set in the

SPISTAT Register as well as the IRQ bit (which indicates that the transaction is complete).

ZUSBOPTSC01ZAC 数据表(PDF) 177 Page - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 177 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载