ZUSBOPTSC01ZAC datasheet(180/402 Pages) ZILOG

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Serial Peripheral Interface

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

158

SPI Control Register

The SPI Control Register configures the SPI for transmit and receive operations.

IRQE—Interrupt Request Enable

0 = SPI interrupts are disabled. No interrupt requests are sent to the Interrupt Controller.

1 = SPI interrupts are enabled. Interrupt requests are sent to the Interrupt Controller.

STR—Start an SPI Interrupt Request

0 = No effect.

1 = Setting this bit to 1 also sets the IRQ bit in the SPI Status register to 1. Setting this bit

forces the SPI to send an interrupt request to the Interrupt Control. This bit can be used by

software for a function similar to transmit buffer empty in a UART. Writing a 1 to the

IRQ bit in the SPI Status register clears this bit to 0.

BIRQ—BRG Timer Interrupt Request

If the SPI is enabled, this bit has no effect. If the SPI is disabled:

0 = The Baud Rate Generator timer function is disabled.

1 = The Baud Rate Generator timer function and time-out interrupt are enabled.

PHASE—Phase Select

Sets the phase relationship of the data to the clock. Refer to the SPI Clock Phase and

Polarity Control section for more information on operation of the PHASE bit.

CLKPOL—Clock Polarity

0 = SCK idles Low (0).

1 = SCK idle High (1).

WOR—Wire-OR (Open-Drain) Mode Enabled

0 = SPI signal pins not configured for open-drain.

1 = All four SPI signal pins (SCK, SS, MISO, MOSI) configured for open-drain function.

This setting is typically used for multi-master and/or multi-slave configurations.

MMEN—SPI MASTER Mode Enable

0 = SPI configured in SLAVE mode.

1 = SPI configured in MASTER mode.

Table 85. SPI Control Register (SPICTL)

BITS

FIELD

IRQE

STR

BIRQ

PHASE

CLKPOL

WOR

MMEN

SPIEN

RESET

00H

R/W

ADDR

F61H

ZUSBOPTSC01ZAC 数据表(PDF) 180 Page - Zilog, Inc.

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