ZUSBOPTSC01ZAC datasheet(183/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

SPI Diagnostic State Register

Z8FMC16100 Series Flash MCU

Product Specification

161

000 = 8 bits

001 = 1 bit

010 = 2 bits

011 = 3 bits

100 = 4 bits

101 = 5 bits

110 = 6 bits

111 = 7 bits

SSIO—Slave Select I/O

0 = SS pin configured as an input.

1 = SS pin configured as an output (MASTER mode only).

SSV—Slave Select Value

If SSIO = 1 and SPI configured as a Master:

0 = SS pin driven Low (0).

1 = SS pin driven High (1).

This bit has no effect if SSIO = 0 or SPI configured as a Slave

SPI Diagnostic State Register

The SPI Diagnostic State Register provides observability of internal state. It is a read-only

SCKEN - Shift Clock Enable

0 = The internal Shift Clock Enable signal is deasserted

1 = The internal Shift Clock Enable signal is asserted (shift register is updates on next sys-

tem clock)

TCKEN - Transmit Clock Enable

0 = The internal Transmit Clock Enable signal is deasserted.

1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial

data out is updated on the next system clock (MOSI or MISO).

Table 88. SPI Diagnostic State Register (SPIDST)

BITS

FIELD

SCKEN

TCKEN

SPISTATE

RESET

00H

R/W

ADDR

F64H

ZUSBOPTSC01ZAC 数据表(PDF) 183 Page - Zilog, Inc.

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