ZUSBOPTSC01ZAC datasheet(187/402 Pages) ZILOG

187 / 402 page

PS024604-1005

P R E L I M I N A R Y

I2C Master/Slave Controller Registers

Z8FMC16100 Series Flash MCU

Product Specification

165

I2C Master/Slave Controller Registers

Table 91 summarizes the I2C master/slave controller’s software-accessible registers.

Comparison with the Master Mode Only I2C Controller

Porting code written for the MASTER ONLY I2C controller found on other Z8 Encore!®

parts to the I2C Master/Slave Controller is straightforward. The I2CDATA, I2CCTL,

I2CBRH and I2CBRL Register definitions have not changed. The following bullets high-

light the differences between these two designs.

• The Status (I2CSTATE) Register from the MASTER ONLY I2C controller is split into

the Interrupt Status (I2CISTAT) Register and the State (I2CSTATE) Register because

more interrupt sources are available. The ACK, 10B, TAS (now called AS), and DSS

(now called DS) bits, formerly part of the Status Register, are now part of the State Reg-

ister.

• The I2CSTATE Register was called the Diagnostic State (I2CDST) Register in the

MASTER-mode-only version. The I2CDST Register provided diagnostic information.

The I2CSTATE Register contains status and state information that may be useful to

software in an operational mode.

• The I2CMODE Register was called the Diagnostic Control (I2CDIAG) Register in the

MASTER-mode-only version. The I2CMODE Register provides control for the

SLAVE modes of operation, as well as the most significant two bits of the 10-bit slave

address.

Table 91. I2C Master/Slave Controller Registers

Name

Abbreviation Description

I2C Data

I2CDATA

Transmit/receive data register.

I2C Interrupt Status I2CISTAT

Interrupt status register.

I2C Control

I2CCTL

Control register—basic control functions.

I2C Baud Rate High I2CBRH

High byte of baud rate generator initialization

value.

I2C Baud Rate Low I2CBRL

Low byte of baud rate generator initialization

value.

I2C State

I2CSTATE

State register.

I2C Mode

I2CMODE

Selects MASTER or SLAVE modes, 7- or 10-bit

addressing; configure address recognition, define

slave address bits [9:8].

I2C Slave Address

I2CSLVAD

Defines slave address bits [7:0].

ZUSBOPTSC01ZAC 数据表(PDF) 187 Page - Zilog, Inc.

ZUSBOPTSC01ZAC 数据表(HTML) 187 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载