ZUSBOPTSC01ZAC datasheet(191/402 Pages) ZILOG

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PS024604-1005

P R E L I M I N A R Y

Start and Stop Conditions

Z8FMC16100 Series Flash MCU

Product Specification

169

Start and Stop Conditions

The master generates the START and STOP conditions to start or end a transaction. To

start a transaction, the I2C controller generates a START condition by pulling the SDA sig-

nal Low while SCL is High. To complete a transaction, the I2C controller generates a

STOP

condition by creating a Low-to-High transition of the SDA signal while the SCL

signal is High. These START and STOP events occur when the START and STOP bits in

the I2C Control Register are written by software to begin or end a transaction. Any byte

transfer currently under way, including the Acknowledge phase, finishes before the

START or STOP condition occurs.

Software Control of I2C Transactions

The I2C controller is configured via the I2C Control and I2C Mode registers. The

MODE[1:0]

field of the I2C Mode Register allows the configuration of the I2C controller

for MASTER/SLAVE or SLAVE ONLY mode, and configures the slave for 7- or 10-bit

addressing recognition.

MASTER/SLAVE mode can be used for:

• MASTER ONLY operation in a single master/one or more slave I2C system

• MASTER/SLAVE in a multimaster/multislave I2C system

• SLAVE ONLY operation in an I2C system

In SLAVE ONLY mode, the START bit of the I2C Control Register is ignored (software

cannot initiate a master transaction by accident), and operation to SLAVE ONLY mode is

restricted, thereby preventing accidental operation in MASTER mode.

The software can control I2C transactions by enabling the I2C controller interrupt in the

interrupt controller or by polling the I2C Status Register.

To use interrupts, the I2C interrupt must be enabled in the interrupt controller and followed

by executing an EI instruction. The TXI bit in the I2C Control Register must be set to

enable transmit interrupts. An I2C interrupt service routine then checks the I2C Status

To control transactions by polling, the TDRE, RDRF, SAM, ARBLST, SPRS, and NCKI inter-

rupt bits in the I2C Status Register should be polled. The TDRE bit asserts regardless of the

state of the TXI bit.

Master Transactions

The following sections describe master Read and Write transactions to both 7- and 10-bit

slaves.

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