ZUSBOPTSC01ZAC datasheet(190/402 Pages) ZILOG

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I2C Master/Slave Controller

P R E L I M I N A R Y

PS024604-1005

Z8 Encore!® Motor Control Flash MCUs

Product Specification

168

Address (GCA) bit of the I2CISTAT Register indicates whether the address match occurred

on the unique slave address or the General Call/STARTBYTE address. The SAM bit clears

automatically when the I2CISTAT Register is read.

If configured via the MODE[1:0] field of the I2C Mode Register for 7-bit slave address-

ing, the most significant 7 bits of the first byte of the transaction are compared against the

SLA[6:0]

bits of the Slave Address Register. If configured for 10-bit slave addressing,

the first byte of the transaction is compared against {11110,SLA[9:8],R/W} and the sec-

ond byte is compared against SLA[7:0].

Arbitration Lost Interrupts

Arbitration Lost interrupts (ARBLST bit = 1 in I2CISTAT) occur when the I2C controller is

in MASTER mode and loses arbitration (outputs a 1 on SDA and receives a 0 on SDA).

The I2C controller switches to SLAVE mode when this instance occurs. This bit clears

automatically when the I2CISTAT Register is read.

Stop/Restart Interrupts

A Stop/Restart event interrupt (SPRS bit = 1 in I2CISTAT) occurs when the I2C controller

is in SLAVE mode and a STOP or RESTART condition is received, indicating the end of the

transaction. The RSTR bit in the I2C State Register indicates whether the bit was set due to

a STOP or RESTART condition. When a restart occurs, a new transaction by the same mas-

ter is expected to follow. This bit is cleared automatically when the I2CISTAT Register is

read. The STOP/RESTART interrupt only occurs on a selected (address match) slave.

Not Acknowledge Interrupts

Not Acknowledge interrupts (NCKI bit = 1 in I2CISTAT) occur in MASTER mode when a

Not Acknowledge is received or sent by the I2C controller and the START or STOP bit is

not set in the I2C Control Register. In MASTER mode, the Not Acknowledge interrupt

clears by setting the START or STOP bit. When this interrupt occurs in MASTER mode,

the I2C controller waits until it is cleared before performing any action. In SLAVE mode,

the Not Acknowledge interrupt occurs when a Not Acknowledge is received in response to

data sent. The NCKI bit clears in SLAVE mode when software reads the I2CISTAT Regis-

ter.

General Purpose Timer Interrupt from Baud Rate Generator

If the I2C controller is disabled (IEN bit in the I2CCTL Register = 0) and the BIRQ bit in

the I2CCTL Register = 1, an interrupt is generated when the baud rate generator (BRG)

counts down to 1. The baud rate generator reloads and continues counting, providing a

periodic interrupt. None of the bits in the I2CISTAT Register are set, allowing the BRG in

the I2C controller to be used as a general-purpose timer when the I2C controller is dis-

abled.

ZUSBOPTSC01ZAC 数据表(PDF) 190 Page - Zilog, Inc.

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